`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/24 23:44:43
// Design Name: 
// Module Name: Hex_7_Seg
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Hex_7_Seg(
    input [15:0] number,
    input clk,
    input rst, 

    input [3:0] len,

    output reg[3:0] an,
    output reg[6:0] a_to_g
    );

    wire [1:0] s;
    reg [3:0] digit;
    reg [19:0] clkdiv  = 8'b0;//[7:0]  clkdiv;    //


    always @(*) begin
        case(s)
            0:digit = number[3:0];
            1:digit = number[7:4];
            2:digit = number[11:8];
            3:digit = number[15:12];
            default :digit = number[3:0];         
        endcase
    end

    


    always @(*) begin
        case (digit)
            0:a_to_g = 7'b1111110;
            1:a_to_g = 7'b0110000;
            2:a_to_g = 7'b1101101;
            3:a_to_g = 7'b1111001;
            4:a_to_g = 7'b0110011;
            5:a_to_g = 7'b1011011;
            6:a_to_g = 7'b1011111;
            7:a_to_g = 7'b1110000;
            8:a_to_g = 7'b1111111;
            9:a_to_g = 7'b1111011;
            'hA:a_to_g = 7'b1110111;
            'hB:a_to_g = 7'b0011111;
            'hC:a_to_g = 7'b1001110;
            'hD:a_to_g = 7'b0111101;
            'hE:a_to_g = 7'b1001111;
            'hF:a_to_g = 7'b1000111;
            default: a_to_g = 7'b1111110;
                
        endcase
    end


    always @(posedge clk) begin
        if(rst == 1)begin
            clkdiv <=0;
        end
        else begin
            clkdiv <= clkdiv + 1;
        end
    end

    always @(*) begin
        an = 4'b0000;
        an[s] = 1& (~rst) & len[s];
    end


    assign s=clkdiv[19:18]; //clkdiv[7:6];    //


endmodule
